1. Field of the Invention
The present invention relates to power distribution for integrated circuits (ICs). More specifically, the present invention relates to power distribution for ICs connected to printed circuit boards (PCBs).
2. Description of the Related Art
In recent years, high speed operation of electronic circuit devices has been demanded and research thereon has been carried out. Electronic circuit devices that can operate at high speed would enable the time of processing, which formerly took a long time, to be shortened drastically, would allow processing formerly considered impossible to be performed, and would make it possible to execute a large number of tasks with one device instead of multiple devices, thus reducing processing costs and contributing to development of services, facilities, functions, etc.
The supply voltage of an electronic circuit should not substantially change over time. Even though the electronic circuit's consumption of current does substantially fluctuate over short periods of time, if the supply voltage substantially changes, the electronic circuit, including ICs, will malfunction. The basic power distribution task can be simply stated as: the power distribution must support load current across the load signal spectrum while maintaining the load voltage within acceptable limits for reliable operation. If the supply voltage substantially changes, the electronic circuit, including ICs, can be unable to maintain normal operation, and the output voltage of the electronic circuit can change, making it impossible to provide normal output signals. The change of output voltage can be interpreted as noise in the output signals. If the noise is large, the electronic circuit can even malfunction.
For this reason, the power distribution system and the power wiring system are designed to have a low impedance. These systems are designed not only to have a low direct current (DC) resistance, but also to have a low impedance with respect to alternating current (AC) or high frequency signals. If the impedance of the power distribution system and power wiring system is low, even when the consumption current of the circuit fluctuates, the fluctuation of the supply voltage is small and the noise of the circuit is also small. The electronic circuit can operate normally, and therefore, the device, including the electronic circuit, operates normally.
Assuming that the impedance of the power distribution system and power wiring system is Z and that a fluctuation of the circuit's consumption current is ΔI, a supply voltage fluctuation ΔV is represented byΔV=Z·ΔI 
Because a part of this becomes a noise signal, a noise voltage Vn is represented by, where k is a coefficient of 0 to 1:Vnoise=k·ΔV=kZ·ΔI. 
As can be seen from these expressions, if the impedance Z of the power distribution system and power wiring system is small, the supply voltage fluctuation ΔV and noise voltage Vnoise are also small. Therefore, the electronic circuit, including any ICs, can operate normally.
Most current ICs make little attempt to control damping between the reactive elements in the IC, IC die, and in-package capacitance and the largely inductive path between the IC internal power connections and the remainder of the application PCB level power delivery system. Further, the total inductance is a function of individual PCB design. This leaves the cut-off frequency and the damping factor of the inherent IC package low-pass filter dependent on the application PCB design. If the PCB power delivery system impedance is inductive, and/or if the PCB power distribution system (sometimes referred to as power network wiring) resistive impedance is too low, then undesirable resonance occurs within the IC package.
Various techniques have been used to lessen the impedance of the power distribution system and the power wiring system (which will be hereinafter referred to simply as the power distribution system). These various techniques include:
1. finely spaced filter zeroes;
2. high loss dielectric;
3. high skin loss interconnect;
4. using high equivalent series resistance (ESR) capacitors;
5. using bypass capacitors;
6. increasing cross-section of power wires; and
7. distributed RC networks to damp the inherent poles.
The use of finely spaced filter zeroes is discussed by Larry Smith and is essentially an implementation of techniques described by Baudendistel, in “Power Bus Decoupling on Multilayer Printed Circuit Boards”, TR94-8-023, University of Missouri-Rolla Electromagnetic Compatibility Laboratory, May 1994, which is discussed below.
High loss dielectric is an insulator material used in power wiring that absorbs energy by way of the work done by a changing electric field turning molecular dipoles in the high loss dielectric material. It appears as a frequency dependent resistance across the power rails, absorbing more energy at high frequency than at low frequencies. This is discussed, for example, in Novak '258 (U.S. Pat. No. 6,104,258) and Novak '774 (U.S. Pat. No. 6,727,774), discussed below.
High skin loss increases the power wiring impedance. On the one hand, this decreases the power distribution system's ability to deliver current, locally increasing the noise amplitude. On the other hand, because high skin loss is dissipative, it suppresses resonance in the power wiring network and suppresses noise propagation.
High ESR capacitors flatten the impedance of a given capacitor and provide dissipative shunt loss. For a signal spectrum with a flat maximum amplitude, a network with a constant impedance ideally results in peak to peak noise one half of a network with the same high frequency impedance, but where the impedance at middle or low signal frequencies is much lower, for example, at a ratio of 5:1, than at high frequencies. The relationship of lower impedance at low frequency(s) versus higher frequency gives rise to a noise high-pass function. The application of a pulse to a high pass filter where the pulse is substantially longer than the filter's time constant affects proximate differentiation of the noise pulse. The noise consists of an impulse at the leading edge, and an impulse at the trailing edge, each of similar magnitude set by the high frequency shunt impedance. For a pulse significantly longer than the filter time constant, the leading impulse recovers close to zero prior to the opposing impulse. When the impedance is constant, the response is simply that of a scalar, deflecting from zero for the duration of the pulse and recovering to zero at the end of the pulse. When the ESR of a capacitor is high, the ESR dominates capacitor impedance over a broad frequency range and makes it easier to avoid the high pass noise filter characteristic common to filters made with low ESR capacitors.
A technique of using bypass capacitors and a technique of increasing a cross-section of the power wiring are widely used prior art techniques.
A bypass capacitor is a capacitor of substantial capacity connected between two power wires. Power is always supplied on two or more wires, such as 5 V (volts) and ground; the bypass capacitor is connected between the two wires. If three or more wires, such as 5 V, 3 V, and ground, are used, the bypass capacitor is connected between two wires such as the 5 V wire and ground or the 3 V wire and ground. The bypass capacitor is often connected between ground and other wires, but it is not necessary to provide for all combinations of wires.
A theoretical capacitor, which by its nature has an impedance that decreases as frequency increases, has an effect of reducing the impedance of the power distribution system in alternating current or high frequency signal situations. A theoretical inductor, which by its nature has an impedance that increases as frequency increases, has an effect of increasing the impedance of the power distribution system in alternating current or high frequency signal situations. Therefore, at equal cost and complexity, it is desirable to construct the power distribution system so as to not exhibit any significant inductive characteristic within the load current spectrum.
Normally, in a power distribution system, a voltage regulator unit (alternatively, a voltage regulator module (VRM)) and an electronic circuit, including any ICs, are connected by electric wiring. A typical arrangement of the power distribution system is shown in FIG. 11. An IC package 10 and a voltage regulator module 13 are mounted on a PCB 12. The IC package 10 includes a die 11.
A power distribution system impedance for an alternating current or high frequency situation viewed from the electronic circuit increases because of the inductance of the wiring connecting the electronic circuit and the power distribution system. Then, when a bypass capacitor is connected near the electronic circuit, the power distribution system impedance viewed from the electronic circuit decreases. Particularly, for high speed electronic circuits, the high frequency characteristic of the power distribution system impedance must be low.
A bypass capacitor typically is located very near the electronic circuit for decreasing the inductance between the electronic circuit and the bypass capacitor. When a plurality of electronic circuits exists, a bypass capacitor typically is provided sufficiently close to each electronic circuit or for each group of a small number of electronic circuits. This power distribution system impedance reduction technique using bypass capacitors reduces the power distribution system impedance for alternating current or high frequency signals as viewed from the electronic circuit, although the impedance of the wiring connecting the electronic circuit and the power distribution system remains unchanged and in many cases dominates the power distribution impedance.
Another power distribution system impedance reduction technique is to increase a cross-section of the power distribution wiring in order to reduce power distribution wiring inductance and power distribution system impedance. To effectively carry out this technique, the power distribution wiring is often made wide, specifically, in the shape of a plane. For example, with printed circuit boards and other similar devices, a multilayer structure is adopted to provide a power distribution layer, and the power distribution wiring in this power distribution layer is made flat. Often, through holes are required for connecting parts and wires, and the plane of the power distribution layer is perforated like a mesh. Generally, because at least one of the power distribution wires is ground, ground is also contained in the power distribution wiring.
If the power distribution wiring is formed like a plane, the inductance of the power distribution wiring in the circuit board and that of the power distribution wiring between the bypass capacitor and electronic circuit can be lowered drastically, enabling reduction of the power distribution system impedance for alternating current or high frequency signals.
Another technique is to reduce the spacing between the power distribution wires (vertical separation in the case of planar wires) to reduce the inductance, which is similar to the technique of reducing the inductance by increasing the width of the power distribution wires.
The two power distribution system impedance reduction techniques, increasing the cross-section of the power wiring and reducing spacing between power distribution wiring, described above can be used in combination and often are used in combination. These techniques are compatible with each other for reducing the power distribution system impedance.
Prior art techniques also include gross application of distributed R-L-C networks that attempt to realize a net flat to low-pass noise transfer function for power distribution systems that rely upon power planes.
Baudendistel (“Power Bus Decoupling on Multilayer Printed Circuit Boards,” TR94-8-023, University of Missouri-Rolla Electromagnetic Compatibility Laboratory, May 1994) discloses how to determine values of damping elements used to suppress power distribution system resonances, which cause high impedances within the power distribution bandwidth. For low frequencies where the impedance of the power plane cavities (LPLN) is low and where the resistance of the plane (RPLN) is also low, Baudendistel uses a simple one-dimensional approximation to estimate power distribution system behavior up to the resonance between the bypass capacitor network and any power plane cavity.
Baudendistel's model consists of n parallel RLC branches as shown in FIG. 1. The relationship between the frequency and the impedance, Z, based upon this model is shown in FIG. 2. Each branch represents the parallel aggregate for a particular capacitor value. Each parameter, RVALi, LVALi, and CVALi, where i=1, . . . , n, represents the parallel equivalent of the respective value from each device. For example, given ten instances of 1 μF, 2 mΩ, 1 nH capacitors, the branch is represented by a 10 μF, 0.2 mΩ, 0.1 nH capacitor. The parallel plate capacitance of the power/ground wiring cavity is represented by a single capacitor, CPLN.
As seen in FIG. 3, Baudendistel reduces the peaks of the resonances by increasing the magnitude of the resistance, Rx, with respect to the corresponding inductance, Lx, where x is one of 1, . . . , n, so as to flatten the impedance transitions from the region in which the impedance is dominated by the (n−1)th inductor (the region that has an upward slope approximated by jωLVALn−1) to the region in which the impedance is dominated by the nt h capacitor (the region that has a downward slope approximated by 1/(jωCVALn)).
Baudendistal enumerates impedance equations for each branch and branches in parallel. Except for the voltage regulator module, VRM, each branch exhibits a series resonant frequency, SRF. The VRM interacts primarily with the branch that has the lowest SRF. At a sufficiently high frequency, the inductive reactance jωLVRM crosses RVRM, as seen on the left side of FIG. 2. The impedance increases to the point where jωLVRM=1/jωCVAL1. Impedance then decreases until the zero where 1/jωCVAL1=jωLVAL1. The residual impedance at this zero is RVAL1. This is best understood by examining the following equation for a given component:Zequivalent=Requivalent+j(ωLequivalent−1/ωCequivalent)where Zequivalent is the total equivalent impedance, Requivalent is the equivalent resistance, Lequivalent is the equivalent inductance, Cequivalent is the equivalent capacitance, j is the imaginary number √−1, and ω is the angular frequency in radians/second. As the frequency increases, jωLVAL1 quickly dominates, increasing the impedance until the pole where jωLVAL1 crosses 1/jωCVAL2. The impedance modulates between zeroes and poles until the last pole at ω=(LVALN*CPLN)−0.5. The extent of impedance modulation depends on the relative quality factor at each zero and pole. The Q factor is the ratio of the inductive reactance to the resistive impedance at the respective pole or zero. A lower Q factor results in less modulation, while a higher Q results in more modulation.
Baudendistal teaches suppression of the impedance peaks at the poles by one or more of the following techniques:
1. Decreasing the series inductance in a given branch or branches;
2. Increasing the series resistance in a given branch or branches; and
3. Increasing the capacitance in the higher frequency branch of a two branch pair forming a pole, thus decreasing the frequency of the pole and jωL.
Lee et al. “Modeling and Analysis of Multichip Module Power Supply Planes,” IEEE Transaction on Components, Packaging and Manufacturing Technology; Part B, Vol. 18, No 4, November 1995) refines the model of Baudendistel by including the distributed effects of the power plane cavities and by including the modal resonances, which are shown on the right hand side of FIG. 7, of the power plane cavities that result from wave reflections at the cavity's boundaries. Specifically, Lee et al. discretizes the power planar cavity into an array of cells as seen in FIGS. 4, 5A-5D, and 6. The cell size is selected to be small compared to the wavelength of the highest frequency of interest (e.g., 1/10th wavelength of the highest frequency of interest or less) in the power distribution system. The cell is then represented either by an equivalent network of resistances, inductances, and capacitance as shown in FIGS. 5A-5D or by a square formed by four intersecting transmission lines as shown in FIG. 6. Lee et al. further suppresses resonances by using thin film materials that exhibit high capacitance and significant distributed damping resistance, i.e., the resistance is distributed over the spatial extent of the structure, as opposed to contained in a localized region or discrete component.
Lee et al. first offers a model using R-L-C equivalents as shown in FIG. 4. Lee et al. derives the inductance and capacitance values from the Telegrapher's Equations. Lee et al. defines three types of cells: interior, edge, and corner as seen in FIGS. 5A-5C.
For computational economy, Lee et al. offers a similar model based on meshed transmission lines, as seen in FIG. 6.
Lee et al. utilizes transmission lines with an impedance of ZINT=√2*(L/C)0.5 inside the outer perimeter and transmission lines with twice the ZINT, 2*√2*(L/C)0.5, around the outer perimeter.
At each interior junction, four lines propagate energy away from any instant source, resulting in an impedance of:ZINT—JUNC=(L/(8C))0.5=H/X*(μ(8∈))0.5.
At each external junction along an edge, the impedance is twice ZINT—JUNC:ZEDG—JUNC=2*ZINT—JUNC=H/X*(μ/(2∈))0.5.
At each corner, the impedance is four times ZINT—JUNC:ZCORNER=4*ZINT—JUNC=H/X*(2μ/∈)0.5.
These impedance values account for neither the loading caused by any attached components nor the density variation caused by arrays of via anti-pads, where anti-pads are perforations in the planes that provide separation between the planes and conductor vias passing through, but not connecting to, those planes.
Novak '258 (U.S. Pat. No. 6,104,258) teaches the addition of termination networks along the perimeter of the cavity defined by the power wiring as a means to match the cavity's interior impedance at the edges so as to suppress the reflections and the resulting modal resonances in the power wiring. Novak '258 teaches that to be effective, the mounted inductance of termination networks should be no more than 0.2 times the inductance of the region terminated.
Novak '258 discloses that the impedance depends on the geometry, permittivity, and permeability of the cavity alone. However, Novak '258 does not account for the loading of the bypass and/or the active components. In situations where the board level components substantially load the power cavity impedance or where the frequency is above the first modal resonance, the method taught by Novak '258 does not match the impedance and will allow substantial reflections.
Instead of the edge termination method taught by Novak '258, Yamamura et al. (U.S. Pat. No. 5,844,762) discloses a distribution of damping elements 14 connected to transmission lines 15 substantially throughout the entire printed circuit assembly, as seen in FIGS. 8A and 8B. Yamamura et al. teaches that an even distribution is ideal.
It can be seen that Yamamura et al. can successfully address branch resonances taught by Baudendistel by merely following Baudendistal's teachings. It can be seen from Lee et al. that Yamamura et al. fails to address the root cause of modal resonances of the power/ground cavity(s): mismatched impedance at the edge boundaries. It can also be seen from Lee et al. that Yamamura et al. can successfully suppress modal resonances in cases where the damping element impedance is both substantially less than the characteristic impedance of the meshed transmission lines and substantially resistive.
By contrast, Novak '258 and Novak '774 (U.S. Pat. No. 6,727,774) teach that to suppress modal resonances, it is sufficient to add termination networks substantially along the PCB boundary so as to match the peripheral impedance to the internal impedance of the plane cavity(s). In doing so, Novak '258 and Novak '774 suppress modal resonances with far fewer components and expense than Yamamura et al.
However, similar to Yamamura et al., Novak '258 and '774 both rely upon achieving a low inductance in the damping elements compared to the plane cavity itself. Novak recites a target inductance in the termination networks of no more than:0.2*μ0*μR*Hwhere μ0 is the permeability of free space (approximately 31.9×10−9 webers/ampere), μR is the relative permeability of the conductors (generally 1.0 webers/ampere or very close to 1.0 webers/ampere), and H is the dielectric thickness within the plane cavity.
For example, given a cavity with a dielectric thickness of 0.001″, the target inductance would need to be <0.2*31.9×10−9 webers/ampere*1 webers/ampere* 0.001 in=6.4 pH. If implemented using common capacitors and if using the planes near the surface of the PCB, the mounted inductance of each capacitor could be about 1 nH, requiring about 160 components. For the case of a power/ground cavity further from the surface of the PCB, such as occurs in a number of complex assemblies, the mounted inductance of each capacitor can be twice as high, requiring double the number of capacitors.
As can be understood from Lee et al., well within an unloaded cavity perimeter, the impedance closely follows:ZINT—JUNC=H/X*(μ/(8∈))0.5.
Well away from the corners along the edges, the impedance closely follows:ZEDG—JUNC=H/X*(μ/(2∈))0.5=2*ZINT—JUNC.
At each corner, the impedance closely follows:ZCORNER=H/X*(2μ/∈)0.5=4*ZINT—JUNC.
As seen in FIG. 9, a dissipative element 17 with resistive impedance of ZEDG—TERM=ZEDG—JUNC (where ZEDG—TERM is the impedance of the dissipative element located on the boundary edge, but not at the corner) is connected to the edge of the transmission lines 18 and nominally reduces the impedance along the boundary edge by half, and thereby matches ZINT—JUNC. In the case of an unloaded, rectangular cavity, this leaves reflections only from the impedance mismatch in the corners where cavity impedance is twice as high as in the center of a given edge.
In order to compensate for the corners, as seen in FIG. 9, the dissipative element 16 is connected to the corner of the transmission lines 18 and must assume a value that is not only substantively lower than the characteristic impedance of the corner itself, but also lower than the impedance in the center of each adjoining edge. Thus, the impedance of the dissipative element 16 located at the corner (ZCORNER—TERM) should be:
                              Z          CORNER_TERM                =                ⁢                  1          /                      (                                          (                                                      X                    /                    H                                    ⋆                                                            (                                              μ                        /                                                  (                                                      8                            ⁢                            ɛ                                                    )                                                                    )                                                              -                      0.5                                                                      )                            -                              (                                                      X                    /                    H                                    ⋆                                                            (                                              2                        ⁢                                                  μ                          /                          ɛ                                                                    )                                                              -                      0.5                                                                      )                                      )                                                  =                ⁢                                            4              /              3                        ⋆                          Z              INT_JUNC                                ⁢                                          =                                    1              /              3                        ⋆                          H              /              X                        ⋆                                                            (                                      2                    ⁢                                          μ                      /                      ɛ                                                        )                                0.5                            .                                          This formula is derived by solving for the parallel impedance in the corner required to maintain a uniform impedance along the boundary.
When uniformly distributed, it can be seen that any bypass components create frequency dependent alterations in the power distribution system impedance. For frequencies below those where the distance is a substantial fraction of the wavelength in the effective dielectric medium, the distributed bypass and wiring networks can be modeled as simpler one-dimensional branches, similar to the model of Baudendistel.
The most troublesome resonance is the transition between the highest frequency R-L-C branch and the lumped power/ground cavity capacitance. For most PCBs, a model of which is shown in FIG. 10 (where transmission lines 19 , bypass elements 20, and IC load 21 are modeled), power/ground cavity capacitance is very limited and set by:C=Area/Height*∈0*∈R 
where C is the capacitance in Farads, Area is the plane cavity surface area, Height is the plane cavity thickness, ∈0 is the permittivity of free space, and ∈R is the relative permittivity of the dielectric material in the plane cavity.
Example capacitances per square inch and impedances for four square inches, which would be typical of a board section occupied by a sizable IC, of a board at several frequencies using typical PCB dielectrics are shown in the following table:
Z in Ohms @ F in MHz,4 inches squareHεRC/sq in10020050010000.0404.022.5 pF 17.78.853.541.770.0104.090.0 pF 4.422.210.880.440.0044.0225 pF1.770.880.350.180.0024.0450 pF0.880.440.180.090.0014.0900 pF0.440.220.090.04
A cavity height of 0.040″ is typical for low cost four or six layer construction. Cavity heights of 0.004″ are typical for processing of complex fiberglass reinforced PCBs.
Given a uniform or nearly uniform distribution throughout a network of bypass capacitors exhibiting a fixed mounted inductance, the transition frequency between the bypass capacitor network and the power/ground cavity of the PCB depends on the following parameters:
1. LCAP—MOUNTED, the mounted inductance of each bypass capacitor;
2. P, the areal density of bypass capacitors;
3. CPLN—SQ—IN, the capacitance per unit area of the power/ground cavity;
4. FRES=P0.5/(2*Π*LCAP—MOUNTED0.5*CPLN—SQ—IN0.5);
5. ZCHAR≈LCAP—MOUNTED0.5/(CPLN—SQ—IN 0.5*P0.5);and
6. ZRES≈LCAP—MOUNTED/(RCAP—MOUNTED*CPLN—SQ—IN);
where FRES is the resonant frequency, ZCHAR is the characteristic impedance of the reactive network consisting of the mounted bypass capacitors and the lumped representation of the power wiring capacitance, and ZRES is the peak impedance at the pole formed from the bypass capacitor network and the lumped power wiring capacitance.
Increasing the bypass capacitor density increases the resonant frequency and decreases the characteristic impedance of the pole formed between the bypass capacitor network and the power/ground cavity of the PCB. However, increasing the capacitor density also reduces resistance per unit area, which increases the impedance peak with respect to the characteristic impedance, i.e., the circuit Q factor is increased.
The prior art methods that have been used to limit ZRES, or the impact of ZRES, include:
1. Increasing the gross density of the bypass capacitors with matching series resistance so as to limit the circuit Q factor, which is described by Baudendistel, Yamamura et al., Novak '258, and Novak '622; or
2. Increasing the capacitance of the power plane cavity.
Each of these methods has serious drawbacks. In the first method, the number of components required can become large, particularly for thick printed circuit assemblies where the distance from the mounting surface of the capacitors and the planes and associated mounted inductance loop can be large.
The second method requires use of expensive and sometimes difficult to handle thin and/or high permittivity dielectric materials. A subtle, potential disadvantage of the second method is that it reduces the resonant frequency between the bypass capacitors and power/ground cavity.
Lee et al. enumerates distributed element modeling of a power distribution system using a two dimensional grid of either discrete R-L-C-G element cells or meshed transmission lines. In a power distribution system model incorporating both Baudendistel and Lee et al., the aggregate bypass capacitor network aggregates to a single R-L-C branch for each value of capacitor used. The value for R is the parallel mounted ESR of all capacitors of the particular value forming the branch. The value for L is similarly the parallel mounted capacitor inductance. Finally, C is the parallel capacitance of the capacitors in the branch.
It can be seen from this model that in order for each damping element to be effective at frequencies where LPLN is significant, the inductance of the damping element, LDAMP, must be small in relation to LPLN. Lee et al. shows that modal resonances occur at frequencies where LPLN is significant.
In the prior art, interposers and modules have been used as component carriers for mechanical, space, and modularity reasons. For example, Alexander et al. (U.S. Pat. No. 6,961,231) discloses an interposer for use with an IC. However, Alexander et al. uses the interposer merely as a means of providing capacitance to supplant the power system. Alexander et al. does not use the interposer to reduce power system impedance, to detune power system resonance, and to redistribute input/output (I/O) to reduce noise injection into the PCB power wiring network caused by discontinuous return paths. The decoupling of the Alexander et al. interposer simply provides some non-specific amount of capacitance. The resonant impedance of two parallel branches is theoretically unaffected by the capacitance of the lower frequency branch. Increasing the capacitance of that branch does not help reduce the troublesome resonance. Adding capacitance to the interposer is only beneficial in reducing resonance between the next lower frequency branch and the interposer. What constitutes that next lower branch depends on both the interposer design and the attached components, such as packaged IC, discrete capacitors, and/or unpackaged IC dice. As such, the additional capacitance disclosed by Alexander et al. may be of little or no benefit to power distribution impedance.
A final problem not recognized or addressed in the prior art is the loading effects of bypass devices and IC loads on the power distribution system. The prior art relies upon a presumption that the power distribution system impedance is low compared to the devices served. As device performance increases in frequency and power, establishing such a distribution system becomes difficult and costly, if not impossible.